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features ? number of keys: ? comms mode: 1 to 12 keys (1 to 9 if wheel or slider option enabled) ? standalone mode: 1 to 5 keys ? technology: ? patented spread-spectrum qtouchadc charge-transfer ? number of output lines: ? comms mode: up to 10 channels can be configured as outputs (but they will replace the keys) ? standalone mode: 1 to 5 channels can be configured as outputs ? key outline sizes: ? 5 mm x 5 mm or larger (panel thickness dependent) ? key spacings: ? 6 mm or wider, center to center (panel thickness, human factors dependent) ? key design: ? single solid or ring shaped electrodes; widely different sizes and shapes possible ? wheel size: ? typically 30 mm-50 mm diameter ? wheel electrode design: ? spatially interpolated wheel up to 80 mm diameter ? typical width of segments 12 mm ? slider electr ode design: ? spatially interpolated, resistorless design ? typical length 50 mm-10 0 mm, typical width 12 mm ? can be an arc or other irregular shape ? substrates: ? fr-4, low cost cem-1 or fr-2 pcb mate rials; polyamide fpcb; pet films, glass ? adjacent metal: ? compatible with grounded me tal immediately next to keys ? layers required: ? one; electrodes and components can be on same side ? electrode materials: ? etched copper, silver, carbon, indium tin oxide (ito), pedot ? panel materials: ? plastic, glass, composites, pain ted surfaces (nonconductive paints) ? key panel thickness: ? up to 15 mm glass (key size dependent) ? up to 10 mm plastic (key size dependent) ? wheel/slider panel thickness: ? up to 4 mm glass ? up to 3 mm plastic ? key sensitivity: ? comms mode ? individually sett able via simple commands over i 2 c-compatible interface ? standalone mode ? settings are fixed ? interface: ?i 2 c-compatible slave mode (400 khz) ? change status indication pin ? signal processing: ? self-calibration, auto drift compen sation, noise filtering, adjacent key suppression ? (aks ? ) ? moisture tolerance: ?good ? power: ? 1.8v to 5.5v ? packages: ? 20-pin soic/tssop rohs compliant ic ? 20-pin vqfn rohs compliant ic qtouch 12-channel touch sensor ic AT42QT2120 preliminary 9634ax?at42?11/11 www.datasheet.co.kr datasheet pdf - http://www..net/
2 9634ax?at42?11/11 AT42QT2120 [preliminary] 1. pinouts and schematics 1.1 pinouts 1.1.1 20-pin soic/tssop ? comms mode 1.1.2 20-pin soic/tssop ? standalone mode key8/gpo6 key7/gpo5 key6/gpo4 key5/gpo3 key4/gpo2 key3/gpo1 key2/gpo0 key1 key0 vss reset change sda n/c key11/gpo9 key9/gpo7 key10/gpo8 vdd mode scl 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 qt2120 out3 out2 key6 key5 key4 key3 key2 guard prox vss reset n/c pxout out6 out4 out5 vdd mode n/c n/c 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 qt2120 www.datasheet.co.kr datasheet pdf - http://www..net/
3 9634ax?at42?11/11 [preliminary] AT42QT2120 1.1.3 20-pin vqfn ? comms mode 1.1.4 20-pin vqfn ? standalone mode vss reset change sda scl 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 qt2120 key8/gpo6 key7/gpo5 key6/gpo4 key5/gpo3 key4/gpo2 key3/gpo1 key2/gpo0 key1 key0 n/c key11/gpo9 key9/gpo7 key10/gpo8 vdd mode vss reset n/c n/c n/c 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 qt2120 out3 out2 key6 key5 key4 key3 key2 guard prox pxout out6 out4 out5 vdd mode www.datasheet.co.kr datasheet pdf - http://www..net/
4 9634ax?at42?11/11 AT42QT2120 [preliminary] 1.2 pin descriptions 1.2.1 20-pin soic/tssop table 1-1. pin listings (20-pin soic/tssop) pin name (comms) name (standalone) type description if unused... 1 key8/ gpo6 out3 i/o comms mode: key 8 / general-purpose output standalone mode: push-pull output for key 3 leave open 2 key7/ gpo5 out2 i/o comms mode: key 7 / general-purpose output standalone mode: push-pull output for key 2 leave open 3 key6/ gpo4 key6 i/o comms mode: key 6 / general-purpose output standalone mode: key 6 leave open 4 key5/ gpo3 key5 i/o comms mode: key 5 / general-purpose output standalone mode: key 5 leave open 5 key4/ gpo2 key4 i/o comms mode: key 4 / general-purpose output standalone mode: key 4 leave open 6 key3/ gpo1 key3 i/o comms mode: key 3 / general-purpose output standalone mode: key 3 leave open 7 key2/ gpo0 key2 i/o comms mode: key/slider/wheel 2 / general-purpose output standalone mode: key 2 leave open 8 key1 guard i/o comms mode: key/slider/wheel 1 standalone mode: guard channel leave open 9 key0 prox i/o comms mode: key/slider/wheel 0 standalone mode: proximity channel leave open 10 vss vss p ground ? 11 vdd vdd p power ? 12 mode mode i mode selection pin comms mode: connect to vss standalone mode: connect to vdd ? 13 sda n/c od comms mode: serial interface data standalone mode: unused pull up to vdd 14 reset reset i active low reset; has internal pull-up 60 k ? resistor tie to vdd 15 n/c pxout o comms mode: no connection standalone mode: open drain output for proximity channel leave open 16 scl n/c od comms mode: serial interface clock standalone mode: unused pull up to vdd 17 change n/c od comms mode: active low s tate change interrupt (external pull-up resistor needed) standalone mode: unused pull up to vdd 18 key11/ gpo9 out6 i/o comms mode: key 11 / general-purpose output standalone mode: push-pull output for key 6 leave open 19 key10/ gpo8 out5 i/o comms mode: key 10 / general-purpose output standalone mode: push-pull output for key 5 leave open 20 key9/ gpo7 out4 i/o comms mode: key 9 / general-purpose output standalone mode: push-pull output for key 4 leave open i input only i/o input and output od open drain output p ground or power www.datasheet.co.kr datasheet pdf - http://www..net/
5 9634ax?at42?11/11 [preliminary] AT42QT2120 1.2.2 20-pin vqfn table 1-2. pin listings (20-pin vqfn) pin name (comms) name (standalone) type description if unused... 1 key6/ gpo4 key6 i/o comms mode: key 6 / general-purpose output standalone mode: key 6 leave open 2 key5/ gpo3 key5 i/o comms mode: key 5 / general-purpose output standalone mode: key 5 leave open 3 key4/ gpo2 key4 i/o comms mode: key 4 / general-purpose output standalone mode: key 4 leave open 4 key3/ gpo1 key3 i/o comms mode: key 3 / general-purpose output standalone mode: key 3 leave open 5 key2/ gpo0 key2 i/o comms mode: key/slider/wheel 2 / general-purpose output standalone mode: key 2 leave open 6 key1 guard i/o comms mode: key/slider/wheel 1 standalone mode: guard channel leave open 7 key0 prox i/o comms mode: key/slider/wheel 0 standalone mode: proximity channel leave open 8 vss vss p ground ? 9vdd vdd ppower ? 10 mode mode i mode selection pin comms mode: connect to vss standalone mode: connect to vdd ? 11 sda n/c od comms mode: serial interface data standalone mode: unused pull up to vdd 12 reset reset i active low reset; has internal pull-up 60 k ? resistor tie to vdd 13 n/c pxout od comms mode: no connection standalone mode: open drain output for proximity channel leave open 14 scl n/c od comms mode: serial interface clock standalone mode: unused pull up to vdd 15 change n/c od comms mode: active low s tate change interrupt (external pull-up resistor needed) standalone mode: unused pull up to vdd 16 key11/ gpo9 out6 i/o comms mode: key 11 / general-purpose output standalone mode: push-pull output for key 6 leave open 17 key10/ gpo8 out5 i/o comms mode: key 10 / general-purpose output standalone mode: push-pull output for key 5 leave open 18 key9/ gpo7 out4 i/o comms mode: key 9 / general-purpose output standalone mode: push-pull output for key 4 leave open 19 key8/ gpo6 out3 i/o comms mode: key 8 / general-purpose output standalone mode: push-pull output for key 3 leave open 20 key7/ gpo5 out2 i/o comms mode: key 7 / general-purpose output standalone mode: push-pull output for key 2 leave open i input only i/o input and output od open drain output p ground or power o output only www.datasheet.co.kr datasheet pdf - http://www..net/
6 9634ax?at42?11/11 AT42QT2120 [preliminary] 1.3 schematics figure 1-1. 20-pin soic/tssop ? comms mode figure 1-2. 20-pin soic/tssop ? standalone mode vss vdd r12 vss vdd scl change r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 key8/gpo6 1 key7gpo5 2 key6/gpo4 3 key5/gpo3 4 key4/gpo2 5 key3/gpo1 6 key2/gpo0 7 key1 8 key0 9 vss 10 vdd 11 mode 12 sda 13 reset 14 n/c 15 scl 16 change 17 key11/gpo9 18 key10/gpo8 19 key9/gpo7 20 sda r13 r14 r15 vdd key 11 key 9 key 7 key 5 key 3 key 1 key 10 key 8 key 6 key 4 key 2 key 0 may be used for wheel or slider vss vdd r12 vdd r6 r5 r4 r3 r2 r1 r0 out3 1 out2 2 key6 3 key5 4 key4 5 key3 6 key2 7 guard 8 prox 9 vss 1 vdd mode 12 n/c 13 reset 14 pxout 15 n/c 16 n/c 17 out6 18 out5 19 out4 20 r13 d key 5 key 3 guard key key 6 key 4 key 2 proximity vdd sensor 0 1 1 vss 1 outputs www.datasheet.co.kr datasheet pdf - http://www..net/
7 9634ax?at42?11/11 [preliminary] AT42QT2120 figure 1-3. 20-pin vqfn ? comms mode figure 1-4. 20-pin vqfn ? standalone mode vss vdd r12 vss vdd scl change vss 8 vdd 9 mode 10 sda 11 reset 12 n/c 15 scl 14 change 15 sda r13 r14 r15 vdd r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 key8/gpo6 19 key7/gpo5 20 key6/gpo4 1 key5/gpo3 2 key4/gpo2 3 key3/gpo1 4 key2/gpo0 5 key1 6 key0 7 key11/gpo9 16 key10/gpo8 17 key9/gpo7 18 key 11 key 9 key 7 key 5 key 3 key 1 key 10 key 8 key 6 key 4 key 2 key 0 may be used for wheel or slider vss vdd r6 r5 r4 r3 r2 r1 r0 out3 19 out2 20 key6 1 key5 2 key4 3 key3 4 key2 5 guard 6 prox 7 vss 8 vdd 9 out6 16 out5 17 out4 18 key 5 key 3 guard key key 6 key 4 key 2 proximity sensor r12 vdd mode 10 n/c 14 reset 12 pxout 13 n/c 15 n/c 11 r13 vdd vss d 1 outputs www.datasheet.co.kr datasheet pdf - http://www..net/
8 9634ax?at42?11/11 AT42QT2120 [preliminary] 2. overview 2.1 introduction the AT42QT2120 (qt2120) is a qtouchadc sensor driver. the device can sense from one to 12 keys, dependent on mode. three of the keys can be used as sense channels for a slider or wheel, leaving a maximum of 9 standard touch keys. the device also supports the use of proximity sensors and a guard channel. the qt2120 includes all signal processing func tions necessary to provide stable sensing under a wide variety of changing conditions, and the outputs are fully debounced. only a few external parts are required for operation and no external cs capacitors are required. the qt2120 modulates its bursts in a spread-spectrum fashion in order to heavily suppress the effects of external noise, and to suppress rf emissions. the qt2120 uses a qtouchadc method of acquisition. this provides greater noise immunity and eliminates the need for external sampling capacitors, allowing touch sensing using a single pin. the qt2120 can operate in two ways; comms and standalone. 2.2 modes 2.2.1 comms mode the qt2120 can operate in comms mode where a host can communicate with the device via an i 2 c-compatible bus. this allows the user to configure settings such as threshold, adjacent key suppression ? (aks ? ), detect integrator, low power (lp) mode, guard channel and max time on for keys. 2.2.2 standalone mode the qt2120 can operate in a standalone mode where an i 2 c-compatible interface is not required. to enter standalone mode, connect the mode pin to vdd before powering up the qt2120. in standalone mode, the start-up values are hard coded in firmware and cannot be changed. the default start-up values are used. this means that key detection is reported via its respective input/output. the guard channel feature is automatically implemented on key 1 in standalone mode. this means that this channel has a higher sensitivity and is used to protect against false triggering, perhaps by a hand covering all keys. a proximity sensor is also available on channel (key) 0 in standalone mode. www.datasheet.co.kr datasheet pdf - http://www..net/
9 9634ax?at42?11/11 [preliminary] AT42QT2120 2.3 keys dependent on mode, the qt2120 can have a minimum of one key and a maximum of 12 keys. these can be constructed in different shapes and sizes. see ?features? on page 1 for the recommended dimensions. the possible combinations of keys are: comms mode: ? 1 to 12 keys or ? 1 to 9 keys plus 1 slider/wheel ? key channels 2 to 11 can be reassigned as general outputs, if required note: any number of keys can be configured as proximity channels. standalone mode: ? 1 to 5 keys plus corresponding discrete outputs ? 1 guard channel ? 1 proximity sensor unused keys should be disabled by setting bit 0 of their control bytes to 1 (see section 5.17 on page 26 ). the key status register (see section 5.5 on page 21 ) can be read to determine the touch status of the corresponding key. it is recommended using the open-drain change line to detect when a change of status has occurred. 2.4 output lines in comms mode some pins, normally used for touc h keys, can be used as output pins. if the key control bit 0 (en) is set to 1, the pin can be used as an output. the state of the pin is then controlled by key control bit 1 (gpo). in standalone mode pins out2 to out6 are driven by key2 to key6 respectively. the out pins drive high during touch and can be used to drive, for example, leds. 2.5 acquisition/low power mode (lp) there are 255 different acquisition times possibl e. these are controlled via the lp mode byte (see section 5.9 on page 22 ) which can be written to via i 2 c-compatible communication. lp mode controls the intervals between acquisi tion measurements. longer intervals consume lower power but have an increased response time. during calibration, touch and during the detect integrator (di) period, the lp mode is temporarily set to lp mode 1 for a faster response. the qt2120 operation is based on a fixed cycle ti me of approximately 16 ms. the lp mode setting indicates how many of these periods ex ist per measurement cycle. for example, if lp mode = 1, there is an acquisition every cycle (16 ms). if lp mode = 3, there is an acquisition every 3 cycles (48 ms). if a high pulse setting is selected then the acquisition time may exceed 16 ms. an lp setting of 0 will send the device into power-down mode. to wake the device from this mode a nonzero lp setting should be written to the lp address at location 8. www.datasheet.co.kr datasheet pdf - http://www..net/
10 9634ax?at42?11/11 AT42QT2120 [preliminary] 2.6 adjacent key suppressi on (aks) technology the device includes atme l?s patented adjace nt key suppression (aks) technology, to allow the use of tightly spaced keys on a keypad wit h no loss of selectability by the user. there can be up to three aks groups, implemented so that only one key in the group may be reported as being t ouched at any one time. once a key in a particular aks group is in detect no other key in that group can go into detect. only when the key in detect goes out of detection can another key go into detect state. keys which are members of the aks groups can be set in the key control register (see section 5.17 on page 26 ). keys outside the group may be in detect simultaneously. note: to use a key as a guard channel, its aks group s hould be set to be t he same as that of the keys it is to protect. 2.7 change line (comms mode only) the change line is active low and signals when there is a change of state in the detection status and/or key status bytes. it is cleared (allowed to float high) when the host reads the status bytes. if the status bytes change back to their original state before the host has read the status bytes (for example, a touch followed by a release), the change line will be held low. in this case, a read to any memory lo cation will clear the change line. the change line is open-drain and should be connected via a 47 k ? resistor to vdd. it is necessary for minimum power operation as it ensures that the qt2120 can sleep for as long as possible. communications wake up the qt2120 from sleep causing a higher power consumption if the part is randomly polled. note: the change line is pulled low 85 ms after power-up or reset. the change line is pulled low approximately 16 ms be fore any bursting on the touch pins will occur. if any of the pins are required to be outputs then the relevant key control settings should be written within this 16 ms time to prevent bu rsting on pins required as outputs. also note that the change line is cleared during a read of the detection status bytes when all bytes differing from the previous read have been read. 2.8 types of reset 2.8.1 external reset an external reset logic line can be used if desired, fed into the reset pin. however, under most conditions it is ac ceptable to tie reset to vdd. the minimum reset pulse width is 2 s. 2.8.2 soft reset the host can cause a device reset by writing a nonzero value to the reset byte. this soft reset triggers the internal watchdog timer on a 125 ms interval. after 125 ms the device executes a full reset. the device nacks any attempts to communicate with it for approximately 200 ms after the soft reset command. communication can begin as soon the the change line is first asserted. note: the device can process a soft reset command while in power down ( lpm = 0) mode, causing a chip reset. www.datasheet.co.kr datasheet pdf - http://www..net/
11 9634ax?at42?11/11 [preliminary] AT42QT2120 2.9 calibration writing a nonzero value to the calibration byte can force a recalibration at any time. this can be useful to clear out a stuck key condition a fter a prolonged period of uninterrupted detection. a calibration command executes 15 burst cycles at lpm 1 and sets the calibrate bit of the detection status register during the calibration sequence. note: a calibration command should be sent whenever key control bit 0 (en) is changed. this changes the use of the key from a standard touch key to an output pin and vice-versa. 2.10 guard channel a guard channel to help prevent false detection is available in both modes. this is fixed on key 1 for standalone mode and programmable for comms mode by setting key control bit 4 (guard) (see section 5.17 on page 26 ). guard channel keys should be more sensitive than the other keys and physically bigger. because the guard channel key is physically bigger it becomes more susceptible to noise so it should have a higher oversampling (see section 5.18 on page 27 ) than the other keys. in standalone mode it is assigned to key 1 and cannot be changed. in comms mode any key can be selected to be a guard key by setting key control bit 4 (guard). the guard channel is connected to a sensor pad which detects the presence of touch. because of its larger size and sensitivity it goes into touch before the keys it surrounds (if, for example, a hand covers all the keys). figure 2-1. guard channel example 2.11 signal processing 2.11.1 detect threshold the device detects a touch when the signal has crossed a threshold level and remained there for a specified number of counts (see section 5.11 on page 24 ). this can be altered on a key-by-key basis using t he key detect threshold i 2 c-compatible commands. this detect threshold is based on the reference value of the particular key. the key?s delta is obtained by subtracting the reference value from the signal value (the signal value rises when touch is present). guard c ha nn e l www.datasheet.co.kr datasheet pdf - http://www..net/
12 9634ax?at42?11/11 AT42QT2120 [preliminary] in standalone mode the detect threshold is set to a fixed value of 10 counts of change with respect to the internal reference level for the guard channel and 10 counts for the other six keys (including proximity channel). the reference level has the abilit y to adjust itself slowly in accordance with the drift compensation mechanism. the drift mechanism will drift toward touch at a rate of 160 ms x 20 = 3.2 seconds (towards touch drift (ttd) register) and away from touch at a rate of 160 ms x 5 = 0.8 seconds (away from touch drift (atd) register). these va lues are fixed in standalone mode but can be configured in comms mode see section 5.10 on page 22 . 2.11.2 detect integrator the device features a fast detection integrator count er (di filter), which acts to filter out noise at the small expense of a slower response time. t he di filter requires a programmable number of consecutive samples confirmed in detection bef ore the key is declared to be touched. the minimum number for the di filter is 1. a setting of 0 for the di also defaults to 1. the di has a maximum usable value of 32. values above this will prevent a key from entering touch. the di is also implemented when a touch is removed. 2.11.3 cx limitations the recommended range for key capacitance cx is 1 pf ? 30 pf. larger values of cx will give reduced sensitivity. 2.11.4 touch recalibration delay if an object or material obstructs the sense pad the signal may rise enough to create a detection, preventing further operation. to prevent this, the sensor includes a timer which monitors detections. if a detection exceeds the timer setting the sensor performs a key recalibration. this is known as the touch recalibration delay (trd) and is set to approximately 30s in standalone mode. in comms mode this feature can be changed by setting a value in the range 1 ? 255 (160 ms ? 40800 ms) in steps of 160 ms. a setting of 0 disables the trd. trd is a global setting and applies to all keys. 2.11.5 away from touch recalibration if a keys signal jumps in the negative direction (with respect to its reference) by more than the away from touch recalibration setting (25 percent of detect threshold), then a recalibration of that key takes place. note: the minimum away from touch recalibration is hard limited to 4 counts. 2.11.6 drift hold time drift hold time (dht) is used to restrict drift on all keys while one or more keys are activated. dht restricts the drifting on all keys until approximately four seconds after all touches have been removed. this feature is particularly useful in cases of high-density keypads where touching a key or hovering a finger over the keypad would cause untouched keys to drift, and therefore create a sensitivity shift, and ultimately inhibit touch detection. in comms mode this value is settable, see section 5.13 on page 24 . www.datasheet.co.kr datasheet pdf - http://www..net/
13 9634ax?at42?11/11 [preliminary] AT42QT2120 the qt2120 will remain in fast mode (lp = 1) for the durati on of the dht counter. the total dht time is 160 ms x dht value. the default setti ng for dht is 25, so 160 ms x 25 = ~4 seconds. the qt2120 will not drift or re-enter slow lp mo de during this time. 2.11.7 hysteresis hysteresis is fixed at 12.5 percent of the detect threshold. when a key enters a detect state once the di count has been reached, the detect threshold (dthr) value is changed by a small amount (12.5 percent of dthr) in the direction away from touch. this is done to effect hysteresis and so makes it less likely a key wi ll dither in and out of detect. dthr is restored once the key drops out of detect. note: the minimum value for hysteresis is 2 counts. 3. wiring and parts 3.1 rs resistors series resistors rs (rs0 ? rs11 for comms mode and rs0 ? rs6 for standalone mode) are in line with the electrode connections and should be used to limit electrostatic discharge (esd) currents and to suppress radio frequency interference (rfi). series resistors are recommended for noise reduction. they should be approximately 4.7 k ?? to 20 k ? each. for maximum noise rejection the value may be up to 100 k ? . care should be taken in this case that the sensor keys are fully charged. the charge time may need to be increased (see section 5.15 on page 25 ). each count increase will extend the charge pulse by approximately 1 s. 3.2 led traces and ot her switching signals digital switching signals near the sense line s induce transients into the acquired signals, deteriorating the signal-to-noise (snr) perform ance of the device. such signals should be routed away from the sensing traces and electrodes, or the design should be such that these lines are not switched during the course of signal acquisition (bursts). led terminals which are multiple xed or switched into a floating state, and which are within, or physically very near, a key (even if on another nearby pcb) should be bypassed to either vss or vdd with at least a 10 nf capacitor. this is to suppress capacitive coupling effects which can induce false signal shifts. the bypass capacitor does not need to be next to the led, in fact it can be quite distant. the bypass capacitor is noncritical and can be of any type. led terminals which are constantly connected to vss or vdd do not need further bypassing. 3.3 pcb cleanliness modern no-clean flux is generally compat ible with capacitive sensing circuits. if a pcb is reworked in any way, clean it thorou ghly to remove all traces of the flux residue around the capacitive sensor components. dry it thoroughly before any further testing is conducted. caution: if a pcb is reworked in any way, it is almost guaranteed that the behavior of the no-clean flux will change. this can mean that t he flux changes from an inert material to one that can absorb moisture and dramatically affect capacitive measurements due to additional leakage currents. if so, the circuit can become erratic and exhi bit poor environmental stability. www.datasheet.co.kr datasheet pdf - http://www..net/
14 9634ax?at42?11/11 AT42QT2120 [preliminary] 3.4 power supply see section6.2 on page30 for the power supply range. if the power supply fluctuates slowly with temperature, the device tracks and compens ates for these changes automatically with only minor changes in sensitivity. if the supply voltage drifts or shifts quickly, the drift compensation mechanism is not able to keep up, causing sensitivity anomalies or false detections. the power should be clean and come from a separate regulator if possible. however, this device is designed to minimize the effects of unstable power, and except in extreme conditions should not require a separate low dropout (ldo) regulator. it is assumed that a larger bypass capacitor (like 1 f) is somewhere else in the power circuit; for example, near the regulator. caution: a regulator ic shared with other logic can result in erratic operation and is not advised. a single ceramic 0.1 f bypass capacitor, wit h short traces, should be placed very close to the power pins of the ic. failure to do so can result in device oscillation, high current consumption and erratic operation. www.datasheet.co.kr datasheet pdf - http://www..net/
15 9634ax?at42?11/11 [preliminary] AT42QT2120 4. i 2 c-compatible communications (comms mode only) 4.1 i 2 c-compatible protocol 4.1.1 protocol the i 2 c-compatible protocol is based around access to an address table (see table 5-1 on page 18 ) and supports multibyte reads and writes. the maximum clock rate is 400 khz. see section a on page 37 for an overview of i 2 c-compatible bus operation. 4.1.2 signals the i 2 c-compatible interface requires two signals to operate: ? sda ? serial data ? scl ? serial clock a third line, change , is used to signal when the device has seen a change in the status byte: ? change : open-drain, active low when the device status has changed since the last i 2 c-compatible read. after reading the four status bytes (1) (or all the status bytes which have changed since the previous read), this pin floats (high) again if it is pulled up with an external resistor. if the status bytes change back to their original state before the host has read the status bytes (for example, a touch followed by a release), the change line is held low. in this case, a read to any memory location clears the change line. 4.2 i 2 c-compatible address there is one preset i 2 c-compatible address of ox1c (28). this is not changeable. 4.3 data read/write 4.3.1 address pointer the internal address pointer is initialized to address 0. 4.3.2 writing data to the device the sequence of events required to wr ite data to the device is shown next. 1. detection status byte, key status byte [0], key status byte[1], slider position table 4-1. description of write data bits key description s start condition sla+w slave address plus write bit a acknowledge bit memaddress target memory address within device data data to be written p stop condition sla+w memaddress aa s data a p host to device device to host www.datasheet.co.kr datasheet pdf - http://www..net/
16 9634ax?at42?11/11 AT42QT2120 [preliminary] 1. the host initiates the transfer by sending the start condition 2. the host follows this by sending the slave address of the device together with the write bit. 3. the device sends an ack. 4. the host then sends the memory address within the device it wishes to write to. 5. the device sends an ack. 6. the host transmits one or more data bytes; each is acknowledged by the device (unless trying to write to an invalid address). valid write address are 5 ? 51. 7. if the host sends more than one data byte, they are written to consecutive memory addresses. 8. the device automatically increments the target memory address after writing each data byte. 9. after writing the last data byte, the host should send the stop condition. note: the host should not try to write to addresses outside the range 0x06 to 0x33 (6 ? 51) because this is the limit of the device?s internal memory address. 4.3.3 reading data from the device the sequence of events required to read data from the device is shown next. 1. the host initiates the transfer by sending the start condition 2. the host follows this by sending the slave address of the device together with the write bit. 3. the device sends an ack. 4. the host then sends the memory address within the device it wishes to read from. 5. the device sends an ack if the address to be read from is less than 0x63 otherwise it sends a nack). 6. the host must then send a stop and a start condition followed by the slave address again but this time accompanied by the read bit. note: alternatively, instead of step 6 a repeated start can be sent so the host does not need to relinquish control of the bus. 7. the device returns an ack, followed by a data byte. 8. the host must return either an ack or nack. a. if the host returns an ack, the device subsequently transmits the data byte from the next address. each time a data byte is transmitted, the device automatically increments the internal address. the device continues to return data bytes until the host responds with a nack. b. if the host returns a nack, it should then terminate the transfer by issuing the stop condition. 9. the device resets the internal address to the location indicated by the memory address sent to it previously. therefore, there is no need to send the memory address again when reading from the same location. sla+w memaddress aa s s sla+r a a p host to device device to host p a /a data 1 data 2 data n www.datasheet.co.kr datasheet pdf - http://www..net/
17 9634ax?at42?11/11 [preliminary] AT42QT2120 note: reading the 16-bit reference and signal values is not an automatic operation; reading the first byte of a 16-bit value does not lock the other byte. as a result glitches in the reported value may be seen as values increase from 255 to 256, or decrease from 256 to 255. this device also supports the use of a repeated start condition as an alternative to the stop condition. 4.4 sda, scl the i 2 c-compatible bus transmits data and clock with sda and scl respectively. they are open-drain; that is i 2 c-compatible master and slave devices can only drive these lines low or leave them open. the termination resistors pull the line up to vdd if no i 2 c-compatible device is pulling it down. the termination resistors commonly range from 1 k ? to 10 k ? ? and should be chosen so that the rise times on sda and scl meet the i 2 c-compatible specifications (300 ns maximum for 400 khz operation). 4.5 standalone mode if i 2 c-compatible communications are not required, then standalone mode can be enabled by connecting the mode pin to vdd. see section 2.4 on page 9 for more information. in standalone mode (mode pin connected to vdd at start?up) the chip is configured to specific settings: ? key0 is configured as a proximity channel. if this key goes into detect then pxout is asserted high. ? key1 is configured as a guard channel and should have a pcb layout which reflects this. ? keys2 ? 6 are standard qtouchadc keys and have pins out 2 ? 6 configured to reflect their respective touch status. ? keys1 ? 6 are configured to ha ve the same aks group setting. www.datasheet.co.kr datasheet pdf - http://www..net/
18 9634ax?at42?11/11 AT42QT2120 [preliminary] 5. setups 5.1 introduction the device calibrates and processes signals usi ng a number of algorithms specifically designed to provide for high survivability in the face of adverse environmental challenges. user-defined setups are employed to alter these algorithms to suit each application. these setups are loaded into the device over the i 2 c-compatible serial interfaces. in standalone mode these settings are fixed to predetermined values. table 5-1. internal register address allocation address use bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w 0 chip id chip id = 0x3e (62) r 1 firmware version major version minor version r 2 detection status calibrate overflow ? ? ? ? sdet tdet r 3 key status key7 key6 key5 key4 key3 key2 key1 key0 r 4 reserved key11 key10 key9 key8 r 5 slider position slider position r 6 calibrate calibrate command r/w 7 reset reset command r/w 8 lp low power (lp) mode r/w 9ttd 0 towards touch drift compensation r/w 10 atd 0 away from touch drift compensation r/w 11 di detection integrator r/w 12 trd touch recal delay r/w 13 dht drift hold time r/w 14 slider options en wheel reserved r/w 15 charge time reserved charge time ? 16 key 0 detect threshold detect threshold level for key 0 r/w 17 key 1 detect threshold detect threshold level for key 1 r/w 18 key 2 detect threshold detect threshold level for key 2 r/w 19 key 3 detect threshold detect threshold level for key 3 r/w 20 key 4 detect threshold detect threshold level for key 4 r/w 21 key 5 detect threshold detect threshold level for key 5 r/w 22 key 6 detect threshold detect threshold level for key 6 r/w 23 key 7 detect threshold detect threshold level for key 7 r/w 24 key 8 detect threshold detect threshold level for key 8 r/w 25 key 9 detect threshold detect threshold level for key 9 r/w 26 key 10 detect threshold detect threshold level for key 10 r/w 27 key 11 detect threshold detect threshold level for key 11 r/w 28 key 0 control reserved guard aks gpo en r/w 29 key 1 control reserved guard aks gpo en r/w 30 key 2 control reserved guard aks gpo en r/w www.datasheet.co.kr datasheet pdf - http://www..net/
19 9634ax?at42?11/11 [preliminary] AT42QT2120 31 key 3 control reserved guard aks gpo en r/w 32 key 4 control reserved guard aks gpo en r/w 33 key 5 control reserved guard aks gpo en r/w 34 key 6 control reserved guard aks gpo en r/w 35 key 7 control reserved guard aks gpo en r/w 36 key 8 control reserved guard aks gpo en r/w 37 key 9 control reserved guard aks gpo en r/w 38 key 10 control reserved guard aks gpo en r/w 39 key 11 control reserved guard aks gpo en r/w 40 key 0 pulse scale pulse3 pulse2 pulse1 pulse0 scale3 scale2 scale1 scale0 r/w 41 key 1 pulse scale pulse3 pulse2 pulse1 pulse0 scale3 scale2 scale1 scale0 r/w 42 key 2 pulse scale pulse3 pulse2 pulse1 pulse0 scale3 scale2 scale1 scale0 r/w 43 key 3 pulse scale pulse3 pulse2 pulse1 pulse0 scale3 scale2 scale1 scale0 r/w 44 key 4 pulse scale pulse3 pulse2 pulse1 pulse0 scale3 scale2 scale1 scale0 r/w 45 key 5 pulse scale pulse3 pulse2 pulse1 pulse0 scale3 scale2 scale1 scale0 r/w 46 key 6 pulse scale pulse3 pulse2 pulse1 pulse0 scale3 scale2 scale1 scale0 r/w 47 key 7 pulse scale pulse3 pulse2 pulse1 pulse0 scale3 scale2 scale1 scale0 r/w 48 key 8 pulse scale pulse3 pulse2 pulse1 pulse0 scale3 scale2 scale1 scale0 r/w 49 key 9 pulse scale pulse3 pulse2 pulse1 pulse0 scale3 scale2 scale1 scale0 r/w 50 key 10 pulse scale pulse3 pulse2 pulse1 pulse0 scale3 scale2 scale1 scale0 r/w 51 key 11 pulse scale pulse3 pulse2 pulse1 pulse0 scale3 scale2 scale1 scale0 r/w 52?53 key signal 0 key signal 0 (msbyte) ? key signal 0 (lsbyte) r 54?55 key signal 1 key signal 1 (msbyte) ? key signal 1 (lsbyte) r 56?57 key signal 2 key signal 2 (msbyte) ? key signal 2 (lsbyte) r 58?59 key signal 3 key signal 3 (msbyte) ? key signal 3 (lsbyte) r 60?61 key signal 4 key signal 4 (msbyte) ? key signal 4 (lsbyte) r 62?63 key signal 5 key signal 5 (msbyte) ? key signal 5 (lsbyte) r 64?65 key signal 6 key signal 6 (msbyte) ? key signal 6 (lsbyte) r 66?67 key signal 7 key signal 7 (msbyte) ? key signal 7 (lsbyte) r 68?69 key signal 8 key signal 8 (msbyte) ? key signal 8 (lsbyte) r 70?71 key signal 9 key signal 9 (msbyte) ? key signal 9 (lsbyte) r 72?73 key signal 10 key signal 10 (msbyte) ? key signal 10 (lsbyte) r 74?75 key signal 11 key signal 11 (msbyte) ? key signal 11 (lsbyte) r 76?77 reference data 0 reference data 0 (msbyte) ? reference data 0 (lsbyte) r 78?79 reference data 1 reference data 1 (msbyte) ? reference data 1 (lsbyte) r 80?81 reference data 2 reference data 2 (msbyte) ? reference data 2 (lsbyte) r 82?83 reference data 3 reference data 3 (msbyte) ? reference data 3 (lsbyte) r 84?85 reference data 4 reference data 4 (msbyte) ? reference data 4 (lsbyte) r table 5-1. internal register address allocation (continued) address use bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w www.datasheet.co.kr datasheet pdf - http://www..net/
20 9634ax?at42?11/11 AT42QT2120 [preliminary] 5.2 address 0: chip id chip id: holds the chip id; always 0x3e . 5.3 address 1: firmware version major version : holds the major firmware version (for example revision 1 .5). minor version : holds the minor firmware version (for example revision 1. 5 ). 5.4 address 2: detection status calibrate: this bit is set during a calibration sequence. overflow: this bit is set if the time to acquire all key signals exceeds 16 ms. sdet: this bit is set if any of the slider/wheel channels are in detect. tdet: this bit is set if any of the keys are in detect. note: if the slider or wheel is enable d then the sdet bit will be set when it is in detect. also the relevant key status bit (0 ? 2) and tdet will be set. these bits can be ignored if the sdet bit is set as the slider/wheel takes priority. a change in these bytes will cause the change line to trigger. 86?87 reference data 5 reference data 5 (msbyte) ? reference data 5 (lsbyte) r 88?89 reference data 6 reference data 6 (msbyte) ? reference data 6 (lsbyte) r 90?91 reference data 7 reference data 7 (msbyte) ? reference data 7 (lsbyte) r 92?93 reference data 8 reference data 8 (msbyte) ? reference data 8 (lsbyte) r 94?95 reference data 9 reference data 9 (msbyte) ? reference data 9 (lsbyte) r 96?97 reference data 10 reference data 10 (msbyte) ? reference data 10 (lsbyte) r 98?99 reference data 11 reference data 11 (msbyte) ? reference data 11 (lsbyte) r table 5-2. chip id address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0chip id table 5-1. internal register address allocation (continued) address use bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w table 5-3. firmware version address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1 major version minor version table 5-4. detection status addressbit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 2 calibrate overflow ????sdettdet www.datasheet.co.kr datasheet pdf - http://www..net/
21 9634ax?at42?11/11 [preliminary] AT42QT2120 5.5 addresses 3 ? 4: key status key0 ? key11: these bits indicate which keys are in detection, if any. touched keys report as 1, untouched or disabled keys report as 0. a change in these bytes will cause the change line to trigger. 5.6 address 5: slider position slider position: reports the slider/wheel position. this value is only valid when the sdet bit in the detection status byte is set. a change in this value will cause the change line to assert low. 5.7 address 6: calibrate calibrate command: writing any nonzero value into this address triggers the device to start a calibration cycle. the calibrate flag in the detection status register is set when the calibration begins and clears when the calibration has finished. 5.8 address 7: reset reset command: writing any nonzero value to this address triggers the device to reset. table 5-5. key status address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 3 key7 key6 key5 key4 key3 key2 key1 key0 4 reserved key11 key10 key9 key8 table 5-6. slider position addressbit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 5 slider position table 5-7. calibrate address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 6 calibrate command table 5-8. reset address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 7 reset command www.datasheet.co.kr datasheet pdf - http://www..net/
22 9634ax?at42?11/11 AT42QT2120 [preliminary] 5.9 address 8: low power (lp) mode lp mode: this 8-bit value determines the number of 16 ms intervals between key measurements. longer intervals between measurements yield a lower power consumption but at the expense of a slower response to touch. default: 1 (16 ms between key acquisitions) to wake the device from power-down mode a nonzero lp setting should be written to this address. the qt2120 can also be reset during power-down mode by writing a nonzero value to the reset register (address 7). 5.10 address 9 ? 10: toward touch and away from touch drift (ttd, atd) toward touch drift and away from touch drift : signals can drift because of changes in cx and cs over time and temperature. it is crucial that such drift be compensated for, else false detections and se nsitivity shifts can occur. drift compensation (see figure 5-1 ) is performed by making the reference level track the raw signal at a slow rate, but only while there is no detection in effect. the rate of adjustment must be performed slowly, otherwise legitimate detec tions could be ignored. the parameters can be configured in increments of 0.16s. table 5-9. lp mode address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 8lp mode setting time 0 power down 1 16 ms 2 32 ms 3 48 ms 4 64 ms ...254 4.064s 255 4.08s table 5-10. toward touch and away from touch drift address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 9 0 toward touch drift 10 0 away from touch drift www.datasheet.co.kr datasheet pdf - http://www..net/
23 9634ax?at42?11/11 [preliminary] AT42QT2120 figure 5-1. thresholds and away from touch drift the device drift compensates using a slew-rate limited change to the reference level; the threshold and hysteresis values are slaved to this reference. when a finger is sensed, the signal increases due to capacitance being added to cx. an isolated, untouched foreign object (a coin, or a water film) will cause the signal to drop very slightly due to an enhancement of coupling. once a finger is sensed, the drift compensa tion mechanism ceases since the signal is legitimately detecting an object. drift compensat ion only works when the signal in question has not crossed the negative threshold level. the drift compensation mechanism can be asy mmetric; the drift-compensation can be made to occur in one direction faster than it does in the other simply by changing the ttd and atd setup parameters. this is a global configuration. specifically, drift compensation should be set to compensate faster for decreasing signals than for increasing signals. increasing signals should not be compensated quickly, since an approaching finger could be compensated for pa rtially or entirely before even touching the touchpad (toward touch drift (ttd)). however, an obstruction over the sense pad, for which the sensor has already made full allowance, could suddenly be removed leaving th e sensor with an artificially suppressed reference level and thus become insensitive to touch. in this latter case, the sensor should compensate for the object's removal by lowering the reference level relatively quickly (away from touch drift (atd)). drift compensation and the detection time-outs work together to provide for robust, adaptive sensing. the time-outs provide abrupt changes in reference calibration depending on the duration of the signal 'event'. if atd or ttd is set to 0 then the drift compensation in the respective direction is disabled. note: it is recommended that the drift compensation rate be more than four times the lp mode period. this is to prevent undersampling, which decreases the algorithm's efficiency. default ttd: 20 (3.2s/reference level) default atd: 5 (0.8s/reference level) www.datasheet.co.kr datasheet pdf - http://www..net/
24 9634ax?at42?11/11 AT42QT2120 [preliminary] 5.11 address 11: detect ion integrator (di) di: allows the di level to be set for each key. this 8-bit value controls the number of consecutive measurements that must be confirmed as having passed the key threshold before that key is registered as being in detect. the minimum value for the di filter is 1. a settings of 0 for the di also defaults to 1. default: 4 (maximum = 32) 5.12 address 12: touc h recal delay (trd) if an object unintentionally contacts a key resulting in a detection for a prolonged interval it is usually desirable to recalibrate the key in order to restore its function, perhaps after a time delay of some seconds. the touch recal delay timer monitors such detections; if a detection event exceeds the timer's setting, the key will be automatically recalibrat ed. after a recalibration has taken place, the affected key will once again function normally even if it is still being contacted by the foreign object. this feature is set globally. trd can be disabled by setting it to zero (infin ite timeout) in which case the key will never autorecalibrate during a cont inuous detection (but the host could still command it). trd is set globally, which can range in value from 1 ? 255. trd above 0 is expressed in 0.16s increments. default: 0 (comms) 255 (standalone) 5.13 address 13: dri ft hold time (dht) this is used to restrict drift on all keys while one or more keys are activated. dht defines the length of time the drift is halted after a key detection. when dht = 0, drifting is never suspended, even during a valid touch of another key. this feature is particularly useful in cases of high-density keypads where touching a key or hovering a finger over the keypad would cause untouched keys to drift, and therefore create a sensitivity shift, and ultimately inhibit any touc h detection. it is expressed in 0.16s increments. dht default value: 25 dht range: 0 ? 255 table 5-11. detection integrator address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 11 di table 5-12. touch recal delay address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 12 trd table 5-13. drift hold time address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 13 dht www.datasheet.co.kr datasheet pdf - http://www..net/
25 9634ax?at42?11/11 [preliminary] AT42QT2120 5.14 address 14: slider options en: setting this bit enables a slider or wheel to be configured. only the first three channels (0, 1 and 2) can be used. wheel: setting this bit allows a wheel to be configured. if not set, and en is enabled, it defaults to a slider. the range of both is from 0 ? 255. figure 5-2. slider/wheel settings en default value: 0 wheel default value: 0 5.15 address 15: charge time prolongs the charge-transfer period of signal acquisition by 1 s per count. allows full charge-tra nsfer for keys with heavy rs / cx loading. range: 0?15 default: 0 table 5-14. slider options address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 14 en wheel reserved 0 255 1 to 254 positio n (at 8 bits - 0 to 255 ch0 tips of tria n gles should be spa c ed <=4mm apart. <=4mm <=4mm positio n 0 positio n 86 positio n 170 ch1 ch2 ch2 ch0 ch1 ch2 table 5-15. charge time address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 15 reserved charge time www.datasheet.co.kr datasheet pdf - http://www..net/
26 9634ax?at42?11/11 AT42QT2120 [preliminary] 5.16 address 16 ? 27: de tect threshold (dthr) dthr key 0 ? dthr key 11: these 8-bit values set the threshold value for each key to register a detection. default: 10 counts note: do not use a setting of 0 as this causes a key to go into detection when its signal is equal to its reference. 5.17 addresses 28 ? 39: key control guard: if set to ?1?, this key will act as a guard channel. a key set as a guard key does not affect the detection status or key status register and the change line is not asserted if this key goes into detect. aks: these bits control which keys are included in an aks group. there can be up to three groups, each containing any number of keys (up to the maximum allowed for the mode). a setting of 0 disables aks for that key. each key can have a value betwe en 0 and 3, which assigns it to an aks group of that number. a key may only go into detect when it has the largest signal change of any key in its group. a value of 0 means the key is not in any aks group. gpo: if set to ?0?, this key is a driven-low output. if set to to 1 then the output is driven high. setting this bit only has an effect if the en bit is set to 1. en: if set to ?0?, indicates that this key is to be used as a touch channel. setting this bit to ?1? will disable the key for touch use and make the channel pin an output. note: it is not possible to enable channel 0 or channel 1 as an output. setting the gpo bit will have no effect on these channels. when a change is made to the en bit a calibration cycle may occur because of the change in the signal values. it is recommended to manually initiate a calibration cycle after a ch ange is made to the en bit regardless of this. comms defaults: all key control bytes set to 0x00 standalone defaults: key 0 control byte = 0x00 key 1 control byte = 0x14 key 2 ? 11 control bytes = 0x04 table 5-16. detect threshold address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 16 dthr key 0 :: 27 dthr key 11 table 5-17. key control address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 28 reserved guard aks gpo en :: 39 reserved guard aks gpo en www.datasheet.co.kr datasheet pdf - http://www..net/
27 9634ax?at42?11/11 [preliminary] AT42QT2120 5.18 addresses 40 ? 51: pulse/scale for keys pulse/scale: the pulse/scale settings are used to set up a proximity key. in comms mode the proximity key is set up by configuring a key?s pulse/scale settings via an i 2 c-compatible bus. in standalone mode, default settings make key 0 a proximity key. this cannot be changed. these bits represent two numbers; the low nibble is scale, high nibble is pulse. each acquisition cycle consists signal ac cumulation and signal averaging. pulse determines the number of measurements accumulated, scale the averaging factor. the scale factor (averaging factor) for the accumulated signal is an exponent of 2. blen is the number of measurements accumulated and is an exponent of 2. for example: oversampling is used to enhance the resolution of the analog-to-digital-converter (adc). oversampling theory says that for each additional bit of resolution, n, the signal must be oversampled four times (or 2 2 x n.) if two bits of addition resolution are required then the pulse setting would be 4 (4 2 = 2 4 ). if 3-bits of additional resolution are required the pulse setting would be 6 (4 3 = 2 6 ). here the result of each adc pulse measurement is taken and added to the last. the oversampling theory also states that this accumulated result must be scaled back by a factor of 2 n . the will be the scale value. figure 5-19 shows some of the recommended oversampling settings.* note: other settings are possible but the pulse val ue should never be more than six higher than the scale setting as the signal result is stored in a 16-bit variable. table 5-18. controls for keys address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 40 pulse scale :: 51 pulse scale table 5-19. oversample for ?n? bits sample scaling bits gained (n) 4^n 2^n n --- --- --- 1 1 0 (pulse = 0x0 / scale = 0x00) 4 2 1 (pulse = 0x2 / scale = 0x01) 16 4 2 (pulse = 0x4 / scale = 0x02) 64 8 3 (pulse = 0x6 / scale = 0x03) 256 16 4 (pulse = 0x8 / scale = 0x04) 1024 32 5 (pulse = 0x0a / scale = 0x05) 4096 64 6 (pulse = 0x0c / scale = 0x06) 16384 128 7 (pulse = 0x0e / scale = 0x07) www.datasheet.co.kr datasheet pdf - http://www..net/
28 9634ax?at42?11/11 AT42QT2120 [preliminary] consideration should be taken on the overall effect on timing when setting pulse values. a single pulse takes approximately 90 s to complete. as all keys are acquired sequentially a high-bit gain setting will add considerably to the time ta ken to acquire all channels. figure 5-3. pulse and scale settings standalone mode defaults: key 0 pulse scale = 0x84 key 1 pulse scale = 0x42 key 2 ? 6 pulse scale = 0x00 comms mode defaults: pulse0 ? pulse3 = 0 scale0 ? scale3 = 0 www.datasheet.co.kr datasheet pdf - http://www..net/
29 9634ax?at42?11/11 [preliminary] AT42QT2120 5.19 address 52 ? 75: key signal key signal: addresses 52 ? 75 allow key signals to be read for each key, starting with key 0. there are two bytes of data for each key. these are the key?s 16-bit key signals which are accessed as two 8-bit bytes, stored msbyte first. these addresses are read-only. 5.20 address 76 ? 99: reference data reference data: addresses 76 ? 99 allow reference data to be read for each key, starting with key 0. there are two bytes of data for each key. these are the key?s 16-bit reference data which is accessed as two 8-bit bytes, stored msbyte first. these addresses are read-only. table 5-20. key signal address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 52 msbyte of key signal for key 0 53 lsbyte of key signal for key 0 :: 74 msbyte of key signal for key 11 75 lsbyte of key signal for key 11 table 5-21. reference data address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 76 msbyte of reference data for key 0 77 lsbyte of reference data for key 0 :: 98 msbyte of reference data for key 11 99 lsbyte of reference data for key 11 www.datasheet.co.kr datasheet pdf - http://www..net/
30 9634ax?at42?11/11 AT42QT2120 [preliminary] 6. specifications 6.1 absolute maxi mum specifications 6.2 recommended o perating conditions 6.3 dc specifications vdd -0.5 to +6v max continuous pin current, any control or drive pin 10 ma short circuit duration to ground, any pin infinite short circuit duration to vdd, any pin infinite voltage forced onto any pin -0.5v to (vdd + 0.5) volts caution: stresses beyond those listed under absolute maximum specifications may cause permanent damage to the device. this is a stress rating only and functional operati on of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum specification conditions for extended period s may affect device reliability. operating temperature -40 o c to +85 o c storage temperature -55 o c to +125 o c vdd +1.8v to 5.5v supply ripple+noise 25 mv cx load capacitance per key 1 to 30 pf vdd = 3.3v, cs = 10nf, load = 5 pf, 32 ms default sl eep, ta = recommended range, unless otherwise noted parameter description minimum typical maximum units notes vil low input logic level ? ? 0.2vdd v vih high input logic level 0.7vdd ? vdd + 0.5 v vol low output voltage ? ? 0.6 v voh high output voltage vdd - 0.7v ? ? v iil input leakage current ? ? 1 a www.datasheet.co.kr datasheet pdf - http://www..net/
31 9634ax?at42?11/11 [preliminary] AT42QT2120 6.4 timing specifications parameter description minimu m typical maximum units notes t r response time di setting x 16 ms ? lp mode + (di setting x 16 ms) ms under host control f qt sample frequency 10.5 12.5 khz modulated spread-spectrum (chirp) t d power-up delay to operate/calibration time ? <230 ? ms can be longer if burst is very long. f i2c i 2 c-compatible clock rate ? ? 400 khz ? fm burst modulation, percentage 15 % ? reset pulse width 2 ? ? s 2 s at 1.8v www.datasheet.co.kr datasheet pdf - http://www..net/
32 9634ax?at42?11/11 AT42QT2120 [preliminary] 6.5 mechanical dimensions 6.5.1 AT42QT2120-su ? 20-pin soic 8263as?avr?08/10 attiny40 www.datasheet.co.kr datasheet pdf - http://www..net/
33 9634ax?at42?11/11 [preliminary] AT42QT2120 6.5.2 AT42QT2120-xu ? 20-pin tssop 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 20x , (formerly 20t), 20-lead, 4.4 mm body width, plastic thin shrink small outline package (tssop) c 20x 10/23/03 6.60 (.260) 6.40 (.252) 1.20 (0.047) max 0.65 (.0256) bsc 0.20 (0.008) 0.09 (0.004) 0.15 (0.006) 0.05 (0.002) index mark 6.50 (0.256) 6.25 (0.246) seating plane 4.50 (0.177) 4.30 (0.169) pin 1 0.75 (0.030) 0.45 (0.018) 0o ~ 8o 0.30 (0.012) 0.19 (0.007) dimensions in millimeters and (inches). controlling dimension: millimeters. jedec standard mo-153 ac www.datasheet.co.kr datasheet pdf - http://www..net/
34 9634ax?at42?11/11 AT42QT2120 [preliminary] 6.5.3 AT42QT2120-mmh ? 20-pin vqfn title drawing no. gpc rev. packa g e drawin g contact: p a ck a gedr a wing s @ a tmel.com 20m2 zfc b 20m2, 20-pad, 3 x 3 x 0.85 mm body, lead pitch 0.45 mm, 1.55 x 1.55 mm exposed pad, thermally enhanced plastic very thin quad flat no lead package (vqfn) 10/24/0 8 15 14 1 3 12 11 1 2 3 4 5 16 17 1 8 19 20 10 9 8 7 6 d2 e2 e b k l pin #1 ch a mfer (c 0. 3 ) d e s ide view a1 y pin 1 id bottom view top view a1 a c c0.1 8 ( 8 x) 0. 3 ref (4x) common dimen s ion s (unit of me asu re = mm) s ymbol min nom max note a 0.75 0. 8 0 0. 8 5 a1 0.00 0.02 0.05 b 0.17 0.22 0.27 c 0.152 d 2.90 3 .00 3 .10 d2 1.40 1.55 1.70 e 2.90 3 .00 3 .10 e2 1.40 1.55 1.70 e ? 0.45 ? l 0. 3 5 0.40 0.45 k 0.20 ? ? y 0.00 ? 0.0 8 www.datasheet.co.kr datasheet pdf - http://www..net/
35 9634ax?at42?11/11 [preliminary] AT42QT2120 6.6 marking 6.6.1 AT42QT2120x-su 6.6.2 AT42QT2120x-xu pin 1 identification date code description date code 1x5 qt2120 w=week code w week code number 1-52 where: a=1 b=2 .... z=26 then using the underscore a =27...z =52 part number qt2120 code revision 1.5, prerelease pin 1 identification date code description date code 1x5 2120 w=week code w week code number 1-52 where: a=1 b=2 .... z=26 then using the underscore a =27...z =52 abbreviated part number qt 2120 code revision 1.5, prerelease www.datasheet.co.kr datasheet pdf - http://www..net/
36 9634ax?at42?11/11 AT42QT2120 [preliminary] 6.6.3 AT42QT2120x-mmh 6.7 part number note: ?x? in the part number before the hyphen (-) denotes a preliminary chip. this is removed on release, so the part number will be as given but with the ?x? removed. the part number comprises: at = atmel 42 = touch business unit qt = charge-transfer technology 2120 = (2) capable of slider/wheel, (12) number of channels, (0) variant number au = tqfp chip mu = mlf chip r = tape and reel 6.8 moisture sensiti vity level (msl) date code description w=week code w week code number 1-52 where: a=1 b=2 .... z=26 then using the underscore a =27...z =52 date code 848 15 pin 1 identification code revision 1.5, released shortened part number in hexadecimal ?848? = ?2120? part number description AT42QT2120x-su 20-pin 0.300 inch wide body, soic rohs compliant ic AT42QT2120x-xu 20-pin 4.4 mm body, tssop rohs compliant ic AT42QT2120x-mmh 20-pin 3 x 3 x 0.85 mm body vqfn rohs compliant ic msl rating peak body temperature specifications msl3 260 o c ipc/jedec j-std-020 www.datasheet.co.kr datasheet pdf - http://www..net/
37 9634ax?at42?11/11 [preliminary] AT42QT2120 appendix a. i 2 c-compatible operation a.1 interface bus the device communicates with the host over an i 2 c-compatible bus. the following sections give an overview of the bus; more detailed informati on is available from www.i2c-bus.org. devices are connected to the i 2 c-compatible bus as shown in figure a-1 . both bus lines are connected to vdd via pull-up resistors. the bus drivers of all i 2 c-compatible devices must be open-drain type. this implements a wired ?and? function th at allows any and all devices to drive the bus, one at a time. a low level on the bus is generated when a device outputs a zero. figure a-1. i 2 c-compatible interface buss a.2 transferring data bits each data bit transferred on the bus is accompanied by a pulse on the clock line. the level of the data line must be stable when the clock line is hi gh; the only exception to this rule is for generating start and stop conditions. figure a-2. data transfer a.3 start and stop conditions the host initiates and terminates a data transmissi on. the transmission is initiated when the host issues a start condition on the bus, and is terminated when the host issues a stop condition. between the start and stop conditions , the bus is considered busy. as shown in figure a-3 , start and stop conditions are signaled by changing the level of the sda line when the scl line is high. vcc device 1 device 2 device 3 device n r1 r2 sda scl sda scl data stable data stable data change www.datasheet.co.kr datasheet pdf - http://www..net/
38 9634ax?at42?11/11 AT42QT2120 [preliminary] figure a-3. start and stop conditions a.4 address byte format all address bytes are 9 bits long, consisting of 7 address bits, one read/write control bit and an acknowledge bit. if the read/w rite bit is set, a read operation is performed, otherwise a write operation is performed. when the device re cognizes that it is being addressed, it will acknowledge by pulling sda low in the ninth scl (ack) cycle. an address byte consisting of a slave address and a read or a write bit is called sla+r or sla+w, respectively. the most significant bit of the address byte is transmitted first. the address sent by the host must be consistent with that selected with the option jumpers. figure a-4. address byte format a.5 data byte format all data bytes are 9 bits long, consisting of 8 data bits and an acknowledge bit. during a data transfer, the host generates the clock and the start and stop conditions, while the receiver is responsible for acknowledging the reception. an acknowledge (ack) is signaled by the receiver pulling the sda line low during the ninth scl cycle. if the receiver leaves the sda line high, a nack is signaled. sda scl start stop sda scl addr msb addr lsb r/w ack start 12 789 www.datasheet.co.kr datasheet pdf - http://www..net/
39 9634ax?at42?11/11 [preliminary] AT42QT2120 figure a-5. data byte format a.6 combining address and data bytes into a transmission a transmission consists of a start condition, an sla+r/w, one or more data bytes and a stop condition. the wired ?anding? of the scl line is used to implement handshaking between the host and the device. the device extends the scl low period by pulling the scl line low whenever it needs extra time for proc essing between the data transmissions. note: each write or read cycle must end with a stop condition. when reading, a repeated start is allowed. so s, sla+w, a, s, sla+r, a, data1, a,......,datax, /a, p can be sent. figure 6-1 shows a typical data transmission. note that several data bytes can be transmitted between the sla+r/w and the stop. figure 6-1. byte transmission scl from master sla+r/w 12 789 sda from transmitter aggregate sda data msb data lsb ack data byte sda from receiver stop or next data byte 12 789 12 789 data msb data lsb ack data byte stop sda scl addr msb addr lsb r/w ack start sla+r/w www.datasheet.co.kr datasheet pdf - http://www..net/
40 9634ax?at42?11/11 AT42QT2120 [preliminary] associated documents ? qtan0079 ? buttons, sliders and wheels touch sensors design guide ? qtan0087 ? proximity design guide ? atmel avr3000: qtouch conducted immunity application note revision history revision number history revision a ? november 2011 ? initial release of document for code revision 1.5 www.datasheet.co.kr datasheet pdf - http://www..net/
41 9634ax?at42?11/11 [preliminary] AT42QT2120 notes www.datasheet.co.kr datasheet pdf - http://www..net/
9634ax?at42?11/11 headquarters international atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel: (+1) (408) 441-0311 fax: (+1) (408) 487-2600 atmel asia unit 01-05 & 16, 19f bea tower, millennium city 5 418 kwun tong road kwun tong kowloon hong kong tel: (+852) 2245-6100 fax: (+852) 2722-1369 atmel munich gmbh business campus parkring 4 d- 85748 garching b. munich tel: (+49) 89-31970-111 fax: (+49) 89-3194621 atmel japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (+81) 3-3523-3551 fax: (+81) 3-3523-7581 touch technology division 1560 parkway solent business park whiteley fareham hampshire po15 7ag united kingdom tel: (+44) 844 894 1920 fax: (+44) 1489 557 066 product contact web site www.atmel.com technical support touch@atmel.com sales contact www.atmel.com/contacts literature requests www.atmel.com/literature disclaimer: the information in this document is provided in connection with at mel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in atmel?s terms and conditions of sale located on atmel?s web site, atmel assumes no liability whatsoever and disclaims any express, implied or statutory warranty relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, consequential, punitive, special or incidental damages (including, without limi tation, damages for loss of profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if atmel has been advised of the possibilit y of such damages. atmel makes no representations or warranties with respect to th e accuracy or completeness of the contents of this document and reserves the right to make changes to specif ications and product descriptions at any time without notice. atmel does not make any commitment to update the information contained herein. unless specific ally provided otherwise, atmel products are not suitable for, and shall not be used in, automo tive applications. atmel?s products are not intended, authorized, or warranted for use as componen ts in applications intended to support or sustain life. ? 2011 atmel corporation. all rights reserved. atmel ? , atmel logo and combinations thereof, adjacent key suppression ? , aks ? , qtouch ? and others are registered trademarks, others are trademarks of atmel corporation or its subsidiaries. other terms and product names may be registered trademarks or trademarks of others. www.datasheet.co.kr datasheet pdf - http://www..net/

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